/*
 * Copyright (C) 2018 Unigroup Spreadtrum & RDA Technologies Co., Ltd.
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 * updated at 2018-12-06 15:47:51
 *
 */

#ifndef ANLG_PHY_G0_H
#define ANLG_PHY_G0_H

#define CTL_BASE_ANLG_PHY_G0 0x32390000

#define REG_ANLG_PHY_G0_ANALOG_DPLL_TOP_ANA_DPLL_DUMY      ( CTL_BASE_ANLG_PHY_G0 + 0x0000 )
#define REG_ANLG_PHY_G0_ANALOG_DPLL_TOP_DPLL_CTRL0         ( CTL_BASE_ANLG_PHY_G0 + 0x0004 )
#define REG_ANLG_PHY_G0_ANALOG_DPLL_TOP_DPLL_CTRL2         ( CTL_BASE_ANLG_PHY_G0 + 0x0008 )
#define REG_ANLG_PHY_G0_ANALOG_DPLL_TOP_DPLL_CTRL3         ( CTL_BASE_ANLG_PHY_G0 + 0x000C )
#define REG_ANLG_PHY_G0_ANALOG_DPLL_TOP_DPLL_CTRL4         ( CTL_BASE_ANLG_PHY_G0 + 0x0010 )
#define REG_ANLG_PHY_G0_ANALOG_DPLL_TOP_DPLL_CTRL5         ( CTL_BASE_ANLG_PHY_G0 + 0x0014 )
#define REG_ANLG_PHY_G0_ANALOG_DPLL_TOP_DPLL_CTRL13        ( CTL_BASE_ANLG_PHY_G0 + 0x0018 )
#define REG_ANLG_PHY_G0_ANALOG_DPLL_TOP_REG_SEL_CFG_0      ( CTL_BASE_ANLG_PHY_G0 + 0x001C )

/* REG_ANLG_PHY_G0_ANALOG_DPLL_TOP_ANA_DPLL_DUMY */

#define BIT_ANLG_PHY_G0_ANALOG_DPLL_TOP_ANALOG_DPLL_DUMY_IN(x)   (((x) & 0xFFFF) << 16)
#define BIT_ANLG_PHY_G0_ANALOG_DPLL_TOP_ANALOG_DPLL_DUMY_OUT(x)  (((x) & 0xFFFF))

/* REG_ANLG_PHY_G0_ANALOG_DPLL_TOP_DPLL_CTRL0 */

#define BIT_ANLG_PHY_G0_ANALOG_DPLL_TOP_DPLL0_LOCK_DONE          BIT(18)
#define BIT_ANLG_PHY_G0_ANALOG_DPLL_TOP_DPLL0_N(x)               (((x) & 0x7FF) << 7)
#define BIT_ANLG_PHY_G0_ANALOG_DPLL_TOP_DPLL0_ICP(x)             (((x) & 0x7) << 4)
#define BIT_ANLG_PHY_G0_ANALOG_DPLL_TOP_DPLL0_ICP_FS(x)          (((x) & 0x3) << 2)
#define BIT_ANLG_PHY_G0_ANALOG_DPLL_TOP_DPLL0_SDM_EN             BIT(1)
#define BIT_ANLG_PHY_G0_ANALOG_DPLL_TOP_DPLL0_DIV_S              BIT(0)

/* REG_ANLG_PHY_G0_ANALOG_DPLL_TOP_DPLL_CTRL2 */

#define BIT_ANLG_PHY_G0_ANALOG_DPLL_TOP_DPLL0_NINT(x)            (((x) & 0x7F) << 23)
#define BIT_ANLG_PHY_G0_ANALOG_DPLL_TOP_DPLL0_KINT(x)            (((x) & 0x7FFFFF))

/* REG_ANLG_PHY_G0_ANALOG_DPLL_TOP_DPLL_CTRL3 */

#define BIT_ANLG_PHY_G0_ANALOG_DPLL_TOP_DPLL0_DIV_SEL(x)         (((x) & 0xF) << 14)
#define BIT_ANLG_PHY_G0_ANALOG_DPLL_TOP_DPLL0_CLKDIV_EN          BIT(13)
#define BIT_ANLG_PHY_G0_ANALOG_DPLL_TOP_DPLL0_IL_DIV             BIT(12)
#define BIT_ANLG_PHY_G0_ANALOG_DPLL_TOP_DPLL0_CCS_CTRL(x)        (((x) & 0xFF) << 4)
#define BIT_ANLG_PHY_G0_ANALOG_DPLL_TOP_DPLL0_MOD_EN             BIT(3)
#define BIT_ANLG_PHY_G0_ANALOG_DPLL_TOP_DPLL0_CLKOUT_EN          BIT(2)
#define BIT_ANLG_PHY_G0_ANALOG_DPLL_TOP_DPLL0_RST                BIT(1)
#define BIT_ANLG_PHY_G0_ANALOG_DPLL_TOP_DPLL0_PD                 BIT(0)

/* REG_ANLG_PHY_G0_ANALOG_DPLL_TOP_DPLL_CTRL4 */

#define BIT_ANLG_PHY_G0_ANALOG_DPLL_TOP_DPLL0_CP_OFFSET(x)       (((x) & 0x3) << 5)
#define BIT_ANLG_PHY_G0_ANALOG_DPLL_TOP_DPLL0_CP_EN              BIT(4)
#define BIT_ANLG_PHY_G0_ANALOG_DPLL_TOP_DPLL0_R3_SEL(x)          (((x) & 0x3) << 2)
#define BIT_ANLG_PHY_G0_ANALOG_DPLL_TOP_DPLL0_R2_SEL(x)          (((x) & 0x3))

/* REG_ANLG_PHY_G0_ANALOG_DPLL_TOP_DPLL_CTRL5 */

#define BIT_ANLG_PHY_G0_ANALOG_DPLL_TOP_DPLL0_RESERVED(x)        (((x) & 0xFF))

/* REG_ANLG_PHY_G0_ANALOG_DPLL_TOP_DPLL_CTRL13 */

#define BIT_ANLG_PHY_G0_ANALOG_DPLL_TOP_DPLL0_BIST_EN            BIT(16)
#define BIT_ANLG_PHY_G0_ANALOG_DPLL_TOP_DPLL0_BIST_CNT(x)        (((x) & 0xFFFF))

/* REG_ANLG_PHY_G0_ANALOG_DPLL_TOP_REG_SEL_CFG_0 */

#define BIT_ANLG_PHY_G0_DBG_SEL_ANALOG_DPLL_TOP_DPLL0_DIV_SEL    BIT(4)
#define BIT_ANLG_PHY_G0_DBG_SEL_ANALOG_DPLL_TOP_DPLL0_CLKDIV_EN  BIT(3)
#define BIT_ANLG_PHY_G0_DBG_SEL_ANALOG_DPLL_TOP_DPLL0_CLKOUT_EN  BIT(2)
#define BIT_ANLG_PHY_G0_DBG_SEL_ANALOG_DPLL_TOP_DPLL0_RST        BIT(1)
#define BIT_ANLG_PHY_G0_DBG_SEL_ANALOG_DPLL_TOP_DPLL0_PD         BIT(0)

#endif